n2807 ti im 20070112-s00005 no.a0979-1/10 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LA72702NV overview the LA72702NV is a us tv btsc decoder. features ? with sif circuit, alignment-fr ee* stereo channel separation. * when base band signal input, separation is adjusted by input level. ? dual slave address(80h, 84h). functions ? sif fm-demodulator ? stereo detection ? sap detection ? stereo decoder ? stereo detection sensitivity change function ? sap output select 2-levels ? dbx noise reduction ? sap demodulator ? sap detection sensitivity change function specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum power supply voltage v cc h max 7.0 v allowable power dissipation pd max ta 85 c, mounted on a specified board* 290 mw operating temperature topr -20 to +85 c storage temperature tstg -55 to +150 c * mounted on a specified board: 114.3mm 76.1mm 1.6mm, glass epoxy board operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended operating voltage vacate 5.0 v allowable operating voltage range v cc h op 4.5 to 5.5 v monolithic linear ic btsc decoder for us tv orderin g numbe r : ena0979 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LA72702NV no.a0979-2/10 electrical characteristics at ta = 25 c, v dd = 5.0v ratings parameter symbol conditions min typ max unit current dissipation i cc no signal inflow current at pin 19, default condition 30 40 50 ma sif input level (reference) v i lim fc = 4.5mhz deviation mono (300hz, mod = 100%, pre-emphasis on) ? 25khz (80) (90) (100) db v base band input level (reference) v i limb 100% modulation mono(l+r) : 530mvp-p (300hz, pre-emphasis on) sub(l-r) : 380mvp-p (300hz, dbx-nr on), pilot : 110mvp-p sap : 300mvp-p (300hz, dbx-nr on) mono output level v o mon fm=1khz, 100% mod, 15khz lpf -7.0 -5.5 -4.5 dbv mono distortion thdmon fm=1khz, 100% mod, 15khz lpf 0.15 0.6 % mono frequency characteri stics fcm1 fm=3 khz, 30% mod, pre-emphasis on * measure ratio from fm=1khz level. -2 0 2 db mono s/n ratio snm s=v o mon, n=0% mod, 15khz lpf 55 65 db stereo output level v o st fm=1khz, 100% mod, 15kh z lpf -7.0 -5.5 -4.5 dbv stereo distortion thds fm=1khz, 100% mod, 15khz lpf 0.5 1.0 % stereo frequency characteristics fc s1 fm=3khz, 30% mod, 15khz lpf * measure ratio from fm=1khz level. -2 0 2 db stereo s/n ratio sns s=v o st, n=0% mod, 15khz lpf 50 60 db stereo separation 1 stse1 f=300hz (r /l), 30% mod, 15khz lpf 20 25 db stereo separation 2 stse2 f=3khz (r /l), 30% mod, 15khz lpf 20 25 db stereo detection level-1 v in sd1 except stereo detection ? stereo detection * serial control ?sens hi? pilot (fh)=15.73khz * measure pilot level. 30 38 45 % stereo detection level-2 v in sd2 except stereo detection ? stereo detection * serial control ?sens lo? 38 47 53 % stereo detection hysteresis hyst input mo d. difference at stereo/except stereo det. * serial control ?sens hi? 10 20 30 % sap output level-1 v o sa1 fm=1khz, 100% mod, 15khz lpf * sap-1 (serial control) -14.0 -11.0 -8.0 dbv sap output level-2 v o sa2 fm=1khz, 100% mod, 15khz lpf * sap-2 (serial control) -7.5 -5.5 -3.5 dbv sap distortion thdsa fm=1khz, 100% mod, 15khz lpf 0.7 1.5 % sap s/n ratio snsa s=v o sa2, n=0% mod, 15khz lpf 50 60 db sap detection level-1 v in sa1 except sap sap det. * serial control ?sens hi? sap carrier=5fh only * measure output level. 10 17 24 % sap detection level-2 v in sa2 except sap sap det. * serial control ?sens lo? * measure output level. 17 24 31 % sap detection hysteresis hysa input mod. difference at sap/except sap det. * sap carrier only. * serial control ?sens hi? 2 5 10 % mode output mono modmo input=mono : f=1khz, 0% mod 0.7 1 1.3 v mode output sap modsa input=sap : carrier 1.6 1.9 2.2 v mode output stereo modst input= stereo : pilot 2.5 2.8 3.1 v mode output st + sap modss input=stereo : pilot, sap : carrier 3.5 3.8 4.2 v stereo detect speed (reference ) stdt input=stereo : pilot i 2 c data no-send measure pin 20 voltage change to 2.8v timing from power on (480) (1000) ms sap detect speed (reference ) sapdt sap : carrier i 2 c data no-send measure pin 20 voltage change to 1.9v timing from power on (350) (1000) ms * normally measurement condit ion is input = sif mode (90db v) * " reference " items are reference levels, their specs are no-guarantee.
LA72702NV no.a0979-3/10 package dimensions unit : mm (typ) 3175c mode condition i 2 c data in output mode i 2 c out signal d8 d7 d6 d5 d4 d3 d2 d1 lch pin18 rch pin17 mode condition d8 d7 mode pin20 ? 0 0 0 l r stereo 0 0 0 1 sap sap sap-1 1 0 0 1 sap sap sap-2 0 0 1 0 l+r sap multi-1 1 0 1 0 l+r sap multi-2 ? 1 0 0 l+r l+r f-mono ? 1 0 1 l+r l+r f-mono ? 1 1 0 l+r l+r f-mono stereo + sap ? ? 1 1 off off mute 1 1 3.8v ? 0 0 0 l r stereo ? 0 0 1 l r stereo ? 0 1 0 l r stereo ? 1 0 0 l+r l+r f-mono ? 1 0 1 l+r l+r f-mono ? 1 1 0 l+r l+r f-mono stereo ? ? 1 1 off off mute 1 0 2.8v ? ? 0 0 l+r l+r mono 0 0 0 1 sap sap sap-1 1 0 0 1 sap sap sap-2 0 0 1 0 l+r sap multi-1 1 0 1 0 l+r sap multi-2 mono + sap ? ? 1 1 off off mute 0 1 1.9v ? ? 0 0 l+r l+r mono ? ? 0 1 l+r l+r mono ? ? 1 0 l+r l+r mono mono (0) fix (0) sif (1) base band ? (0) stereo sens lo (1) hi (0) sap sens lo (1) hi ? 1 1 off off mute 0 0 1.0v * : no care sanyo : ssop24(275mil) 7.8 5.6 7.6 0.22 0.65 (0.33) 12 13 24 1 0.5 0.15 1.5max 0.1 (1.3)
LA72702NV no.a0979-4/10 i 2 c control table grp-1 (normally use : group-1 only) d8 d7 d6 d5 d4 d3 d2 d1 condition * 0 0 stereo 0 1 sap 1 0 both 1 1 mute * 0 normal (auto det) 1 forced mono * 0 sap sens lo 1 sap sens hi * 0 stereo sens lo 1 stereo sens hi * 0 sap level-1 1 sap level-2 * 0 sif mode 1 base band mode * 0 fix 1 prohibit (test mode) * : shows initial condition read out data d8 d7 d6 d5 d4 d3 d2 d1 condition 0 0 0 0 0 0 fixed 0 normal 1 sap det 0 normal 1 stereo det test mode condition(reference) when stop condition transform at grp-1 data-end, controlled normal mode. grp-2 is only test condition. usually, these data are no-nee d. their data are no guarantee, except all l condition. d8 d7 d6 d5 d4 d3 d2 d1 condition/monitor position 0 0 0 0 0 0 0 0 normal (usually, fixed) 0 0 0 1 test-1 sif output 0 0 1 0 test-2 sap bpf 0 0 1 1 test-3 (reserved) 0 1 0 0 test-4 st vco 0 1 0 1 test-5 (reserved) 0 1 1 0 test-6 sap monitor 0 1 1 1 test-7 st monitor 1 0 0 0 test-8 pilot cancel monitor 1 0 0 1 test-9 dbx 2.19k lpf 1 0 1 0 test-10 dbx 408 lpf 1 0 1 1 test-11 dbx det 10k lpf 1 1 0 0 test-12 dbx spec 7.6k lpf 1 1 0 1 test-13 dbx spec output 1 1 1 0 test-14 l+r/ll-r monitor 1 1 1 1 test-15 dbx 2.09k lpf blank bits are no-care slave addresses are 80h (1000 000*, at pin8 open/gnd) and 84h (1000 010*, at pin8 h).
LA72702NV no.a0979-5/10 block diagram and application + + 23 19 18 17 1 2 3 4 5 6 8 9 10 0.1 f 0.1 f 1 f + 1 f 4.7k + 1 f + 2.2 f + 10 f + 4.7 f + 4.7 f + 22 f + 4.7 f 100 f mode monitor out v cc 5v 47 f + 0.1 f 0.1 f2.2 f22 f 4.7 f 1 f to 0.33 f 1 f sif signal from tuner + + i 2 c data address control i 2 c clock out(l) mode out regulator mute matrix l+r mute gnd st control address slave address = 80h (1000 000 * ) : pin8 = open/gnd slave address = 84h (1000 010 * ) : pin8 = h spectral rms det spectral det spectral in offset cancel sap l-r/sap lpf dbx processor wide rms det offset cancell st/sap sw -6db pilot level det + 10 f out(r) sap bpf sif demod lpf pilot canceller stereo pll pilot det l-r demod system control i 2 c decode sap demod 4.5m bpf sap det lpf 22 21 20 24 11 12 16 15 14 13 7 0.033 f 0.033 f *560k *: sap sensitivity only pin7. resistor remove.
LA72702NV no.a0979-6/10 pin functions pin no. pin name function dc: voltage ac: level equivalent circuit 1 pcpldet pilot level detect for stero detection dc : 2.4v 2 pc_dc_in ac coupling (input) dc : 2.4v ac : 2.4vp-p 3 pc_dcout ac coupling (output) dc : 2.4v ac : 2.4vp-p 4 pc fil sif offset cancel dc : 2.6v 5 pisif signal input common input at sif, base band dc : 3.7v 6 gnd 7 csapdet sap carrier level detect for sap detection dc : 2.8v 8 addsel slave address change control open/gnd : 80h 5v : 84h dc : 0v continued on next page. 1 40k 40k 160k 1k 500 1k 2 3 1k 1k 1k 2k 70k 7 8 1k 100k 10k 500 1k 5 4 1k 1k
LA72702NV no.a0979-7/10 continued from preceding page. pin no. pin name function dc: voltage ac: level equivalent circuit 9 sda serial data input 10 scl serial clock input 11 pc dbxin offset cancel feedback filter dc: 2.4v 12 pcdetspe spectral band rms detect dc: 2.3v 13 pctimspe dbx spectral detect dc: 2.4v 14 pctnwid wide band rms detect dc: 2.4v 15 pcspecin dbx main signal v/i convert filter dc: 2.4v 16 pc ke6b offset cancel fe edback filter dc: 2.4v ac: 220mvp-p continued on next page. 0v 5v 0v 5v 9 1k 10 1k 5k 11 12 200 1k 5k 13 14 200 1k 10k 15 500 250 500 16
LA72702NV no.a0979-8/10 continued from preceding page. pin no. pin name function dc: voltage ac: level equivalent circuit 17 porch line out r dc: 2.4v ac: 1.4vp-p 18 polch line out l dc: 2.4v ac: 1.4vp-p 19 v cc 20 poled mode out mono = 0.9v sap = 2.0v stereo = 3.0v stereo + sap = 3.8v dc: see right ac: test only 21 pcreg reference voltage dc: 2.4v 22 pmainout offset cancel feedbac k filter dc: 1.6v 23 pcplc pilot level detect for pilot canceller dc: 2.4v continued on next page. 300 300 50k 50k 17 300 300 50k 50k 18 1k 20 23 40k 40k 160k 1k 22 450k 500 21 10k 9.6k 1k 500
LA72702NV no.a0979-9/10 continued from preceding page. pin no. pin name function dc: voltage ac: level equivalent circuit 24 pcptfilt pilot level detect fo r st pll filter dc: 2.4v i 2 c bus serial interface specification (1) data transfer manual this ic adopts control method (i 2 c-bus) with serial data, and controlled by two terminals which called scl (serial clock) and sda (serial data).at first, set up *1 the condition of starting data transfer , and after that, input 8 bit data to sda terminal with synchronized scl terminal clock. the orde r of transferring is first, msb (the most scale of bit), and save the order. the 9th bit takes ack (acknowledge) peri od, during scl terminal takes ?h?, this ic pull down the sda terminal. after transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 defined by scl rise down sda during ?h? period. *2 defined by scl rise up sda during ?h? period. (2) transfer data format after transfer start condition, transfers slave address (1000 000 * ) to sda terminal, control data, then, stop condition (see figure 1). slave address is made up of 7bits, *3 8th bit shows the direction of transferring da ta, if it is ?l? takes write mode (as this ic side, this is input operation mode), and in case of ?h? re ading mode (as this ic side, this is output operation mode). data works with all of bit, transfer the stop condition before stop 8bit transfer, an d to stop transfer, it will be canceled the transfer dates. *3 it is called r/w bit. fig.1 data structure ?write? mode start condition slave address r/w l ack control data ack stop condition fig.2 data structure ?read? mode start condition slave address r/w h ack internal data * ack stop condition ? the output data synchronizes with the clock of scl pin. then, the ack output is made after the output data. bit8 is result of stero det (h : stereo) bit7 is result of sap det (h : sap) bit6 to bit1 are fixed to ?l? (3) initialize this ic is initialized for circuit protection. initial condition is ?0 (all bits) ?. 24 40k 40k 160k 1k
LA72702NV no.a0979-10/10 reference parameter symbol min max unit low level input voltage v il -0.5 1.5 v high level input voltage v ih 2.5 5.5 v low level output current i ol 3.0 ma scl clock frequency f scl 0 100 khz set-up time for a repeated start condition t su : sta 4.7 s hold time start condition. after this peri od, the first clock pulse is generated t hd : sta 4.0 s low period of the scl clock t low 4.7 s rise time of both sda and sdl signals t r 0 1.0 s high period of the scl clock t high 4.0 s fall time of both sda and sdl signals t f 0 1.0 s data hold time t hd : dat 0 s data set-up time t su : dat 250 ns set-up time for stop condition t su : sto 4.0 s bus free time between a stop and start condition t buf 4.7 s definition of timing t hd:sta t su:sta t low t r t f t high t hd:data t su:dat t su:sto t buf scl sda ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.
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